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# 👋 Hi, I'm Verdvana **Senior ASICs Engineer @ Qualcomm** [![Location](https://img.shields.io/badge/Location-Shanghai%2C%20China-blue?style=flat-square)](https://www.google.com/maps/search/Qualcomm+Shanghai) [![Email](https://img.shields.io/badge/Email-verdvana%40outlook.com-orange?style=flat-square)](mailto:verdvana@outlook.com) [![GitHub](https://img.shields.io/badge/GitHub-Verdvana-lightgrey?style=flat-square&logo=github)](https://github.com/Verdvana) *Expert in Digital IC Design, FPGA/MCU Development, and Hardware Innovation.*

💼 Work Experience

Qualcomm (Shanghai) Co., Ltd.

Senior ASICs Engineering Engineer | 2023.12 - Present ASICs Engineering Engineer | 2021.06 - 2023.12 ASICs Engineering Intern | 2020.06 - 2020.09

  • Leading and contributing to complex digital design and verification flows.

山西中谷科技股份有限公司

Hardware Engineer | 2018.04 - 2018.08

  • Focused on industrial-grade hardware design and low-power systems.

🛠 Technical Skills

Domain Tools & Languages
ASIC Design Verilog SystemVerilog Perl Tcl Python
VCS Verdi Design Compiler
FPGA Dev Vivado Quartus ModelSim NiosII
Hardware Altium OrCAD Allegro Multisim
MCU/Emb Keil MDK Keil C51 C Proteus

🚀 Engineering Projects

🎓 Education

  • 西安电子科技大学 (Xidian University) 2018.09 - 2021.06
    • Master of Electronic and Communication Engineering
  • 中北大学 (North University of China) 2013.09 - 2017.07
    • Bachelor of Electronic Science and Technology