Senior ASICs Engineer at Qualcomm.
Architecting high-performance hardware solutions and exploring the frontiers of IC design.
Specialized in Wi-Fi SoC RTL · Low-Power Architecture · EDA Automation
Led RTL design and subsystem integration for Wi‑Fi 6/7/8 SoCs at Qualcomm Shanghai, contributing to 10+ successful tape‑outs across multiple FastConnect platforms.
Worked closely with architecture and power teams to implement low‑power features at RTL level.
Developed Tcl/Perl automation tools to significantly accelerate STA sign‑off and timing closure efficiency.
Next-gen Wi-Fi 8 flagship with ultra-wide 320 MHz bandwidth, UWB integration, and 4K QAM modulation.
High-bandwidth Wi-Fi 8 solution with advanced low-power Hearable BT subsystem (HBS).
Multi-link Wi-Fi 7 platform with dual Bluetooth architecture and cutting-edge RF design.
Cost-optimized Wi-Fi 7 chip delivering flagship features in a compact, low-power design.
Entry-level Wi-Fi 6 SoC with efficient 2×2 MIMO, targeting IoT and mobile platforms.
Developed low-power industrial sensor systems and high-precision multi-layer PCB designs.
Specialized in digital signal processing and hardware architecture. Award-winner in national electronic design contests.
Foundational studies in semiconductor physics, circuit design, and embedded systems. Recognized as an Outstanding Graduate in 2017.