Senior ASICs Engineer at Qualcomm.
Architecting high-performance hardware solutions and exploring the frontiers of IC design.
Focusing on RTL design, subsystem integration, and low-power implementation for WiFi 6/7/8 SoCs. Developed Tcl/Perl automation tools for high-efficiency timing closure.
Developed low-power industrial sensor systems and high-precision multi-layer PCB designs.
Specialized in digital signal processing and hardware architecture. Award-winner in national electronic design contests.
Foundational studies in semiconductor physics, circuit design, and embedded systems. Recognized as an Outstanding Graduate in 2017.